A high-performance, low-power 2.5 × 2.5 /im emitter transistor

Power dissipation becomes a limiting factor for large-scale integration. Thus, power must be reduced without degrading circuit performance. Reducing the emitter size and thereby the transistor area enables one to operate a circuit at low power levels without degrading its frequency response. The present state of photolithography, however, sets a lower limit on emitter size, which is approximately 2. 5 × 10 μm. We describe a scheme for fabricating transistors reproducibly with 2.5×2.5 μm emitters with present photolithographic capabilities. This scheme follows conventional processing through base diffusion. However, after base diffusion, the base window is convered with a layer of SiO /SiO₂/Si₃N₄. A 2.5 × 10 μm emitter window is first opened in the Si₃N₄ layer. A second masking step follows using an emitter pattern of the same size, but rotated 90 degrees to form a cross-pattern. Etching the underlying SiO₂ selectively will result in a 2.5×2.5 μm emitter window. As a result of emitter-size reduction, the current level at which f_T peaks has been reduced from 5 to 2 mA. The level for maximum current gain has also been reduced, from 1 mA to 100 μA. The collector-base and emitter-base capacitances have been reduced from 0.11 to 0. 06 pF and from 0.1 to 0. 04 pF, respectively.