Crystal oscillator with dual amplitude stabilization feedback loop

In this paper crystal oscillator realized in 90 nm Low Leakage UMC CMOS technology is presented. It is based on the Pierce architecture and uses dual feedback loop to limit the amplitude and generate bias point. Dual feedback architecture allows to achieve almost rail to rail signal with low harmonic levels for wide range of supply voltage. Both of those features have positive impact on phase noise level. The oscillator was designed to work with 16 MHz crystal. It can work with supply voltages from 0.6 to 1.8 V and consumes 78.4μA for 1.2 V supply. In typical case phase noise for 1.2 V supply voltage is -160 dBc/Hz at 10 kHz offset.