Analog circuits sizing using the fixed point iteration algorithm with transistor compact models

This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology. They allow to compute transistors sizes and biases based on transistor compact models while respecting designer´s hypotheses. Computed sizes and biases are accurate, and guarantee the correct electrical behavior as expected by the designer. Sizing and biasing operators interface with a Spice-like simulator, allowing possible use of all available compact models for circuit sizing and biasing over different technologies. To illustrate the effectiveness of the proposed algorithm, a folded cascode OTA was efficiently sized with a 130 nm process, then was migrated to a 65 nm technology. Both sizing and migration were performed in a few milliseconds.