Mitigating lower layer failures with adaptive system reconfiguration

Future terascale systems based on sub-22nm technologies will show significant variability and reliability challenges from the transistor to the circuit level. On this upcoming scenario, a reliable system must be built on top of unreliable components, which will degrade and even fail during the normal lifetime of the chip. To achieve this target, we present a high-level reconfiguration approach for future heterogeneous systems that mitigates the possible lower layer shortcomings and adapts the processor to the user´s requirements.