Digital hardware resources for steering a nonlinear interference suppressor

In this paper the requirements and resulting costs for the digital hardware are discussed to steer a nonlinear interference suppression circuit (NIS). This NIS circuit suppresses a strong unwanted RF blocker by exploiting a nonlinear transfer function in a radio receiver. Nonlinear transfer functions enable frequency-independent amplitude discrimination because they do not obey to the principle of superposition. Such an approach is considered because it can save considerable power and cost in the analog front-end of multi-radio devices. But, to this end an investment is required in the digital part of the system. The analysis in this paper leads to an estimated area consumption of 125k gates and 12k SRAM cells resulting in ≈0.25 mm² and ≈100 μW/MHz if implemented in CMOS 65nm. Also the future development of the cost figures is analyzed.