Design of a 6GHz high-gain low noise amplifier

Author

Xusheng Tang ; Fengyi Huang ; Dawei Zhao

Author_Institution

Nat. Mobile Commun. Res. Lab., Southeast Univ., Nanjing, China

Volume

1

fYear

2012

fDate

5-8 May 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents the design of a low noise amplifier in 0.13-μm CMOS technology. The conventional inductive degeneration is applied to reduce the noise figure. The amplifying stage uses the cascode structure to increase the gain and achieve a better isolation. Operated at 1.2V, the simulated gain of the LNA is better than 20 dB while the noise figure is less than 1.8 dB with the bandwidth from 5 GHz to 6 GHz. The core size of the fully-integrated CMOS LNA circuit is 680μm*800μm.

Keywords

CMOS analogue integrated circuits; low noise amplifiers; microwave integrated circuits; CMOS LNA circuit; bandwidth 5 GHz to 6 GHz; frequency 6 GHz; high-gain low noise amplifier design; inductive degeneration; noise figure; size 0.13 mum; size 680 mum; size 800 mum; voltage 1.2 V; Gain; Impedance matching; Low-noise amplifiers; Noise figure; Radio frequency; Transistors; Wireless communication; Low Noise Amplifier (LNA); high frequency; high-gain; low noise figure;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology (ICMMT), 2012 International Conference on

Conference_Location

Shenzhen

Print_ISBN

978-1-4673-2184-6

Type

conf

DOI

10.1109/ICMMT.2012.6229993

Filename

6229993