The VERUS™ Design Verification System

VERUS is a design specification and verification system developed by Compion Corporation. Design verification is the analysis of the interaction of a computer system´s primitives to show that the system meets certain correctness requirements. The system to be verified is described in a formal specification, which includes statements of the correctness requirements. VERUS is a general-purpose eystem, but its primary application has been to verify systeme modeled as state machines. This paper describes the VERUS approach to state machine specifications by developing a simple security example. VERUS software consists primarily of a pareer and a theorem prover. A specification and proof outlines are converted by the pareer into a form usable by the prover. The proof outlines guide the prover in its search for complete, formal proofs. The parser and theorem prover are used together with a good text editor in a tight, quick loop.