Process variation-aware task replication for throughput optimization in configurable MPSoCS

Due to within-die and die-to-die variations, multiple cores in MPSoC have different delay distributions, and hence the problem of assigning tasks to the cores become challenging. This paper targets system level throughput optimization in streaming pipelined MPSoCs under process variation. First, to maximize system level throughput, we make extensive use of data parallelism of the streaming applications to map them to multiple cores available on a chip. In order to tackle the effect of process variation in clock frequency of these cores, and the resulting deterioration in system timing yield, we propose to deploy frequency scaling and configuration selection for each core. We incorporate timing yield constraint during task replication and load balancing for data parallel tasks. The novel contribution of this work is that we perform all these operations simultaneously, and show the benefits of our approach. We present an ILP solution for maximum throughput under process variation and the proposed solution determines the right degree of parallelism at target timing yield. Our proposed ILP formulation is very generic and can be used for task replication of single or multiple tasks, while simultaneously performing optimum load balancing. The results show that the MPSoC system design flows that do not consider one or more than one of the above mentioned design decisions simultaneously, suffer greatly from the design failures and fail to meet strict timing yield and bandwidth constraints. The throughput of such an MPSoC system is also worse than half of the throughput of our proposed system.