Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers - architecture description

In order to assure the Quality of service (QoS) for some real time applications software schedulers tend to raise the OS tick frequency. Most of the times this is not a convenient solution because the imposed additional overhead can lead to a task deadline missing plus an application failure. It is possible to minimize this overhead by performing the task context switch operation in a dedicated hardware component. This paper presents a custom designed architecture with multi pipeline registers and a dedicated hardware scheduler meant to improve context switch and scheduler times compared to traditional software schedulers.