Point and discard: A hard-error-tolerant architecture for non-volatile last level caches

Technology scaling of SRAM and embedded DRAM is increasingly constrained by limitations such as leakage power and silicon area. Emerging non-volatile memory technologies are considered as the potential SRAM/eDRAM alternatives for last-level caches in terms of energy and area savings. Unfortunately, these non-volatile memory technologies usually have limited write endurance. Even worse, process variation causes some cells to wear out much earlier than others. While state-of-the-art error-tolerant techniques such as ECC can handle transient soft errors, we need a new architecture for non-volatile last-level caches whose reliability is mainly challenged by hard errors. This paper presents Point-and-Discard (PAD), a hard-failure-tolerant architecture for non-volatile caches. PAD has no initial performance penalty and ensures gradual performance overhead with small storage overhead. By adopting PAD, the lifetime of non-volatile caches can be improved by 4.6X over the conventional architecture under a typical process variation condition.¹