Rule agnostic routing by using design fabrics

Moore´s law requires the shrinking of physical dimensions of the transistors to roughly half their area every two years. This poses a tremendous challenge on how to print and manufacture these ever-shrinking physical components that make up the transistors and the interconnect - generation after process generation. One aspect of this challenge is that the process rules are exploding in complexity - directly translating into physical design EDA (Electronic Design Automation) tool complexity. Traditional design rules governed the spacing, overlap or alignment of any two layout objects from this set: diffusion, poly, via cut, wire, etc. In this work we propose a solution that relies on grids (aka. Fabrics), models the design rules on those grids and presents them to the EDA tools in such a way that it minimizes the complexity cost on the tools´ side. In an ideal situation, the proposed solution can completely decouple the tools from the process rules, i.e. even if the tools don´t change at all, they´ll still be able to support new process nodes.