• DocumentCode
    565195
  • Title

    Executing synchronous dataflow graphs on a SPM-based multicore architecture

  • Author

    Choi, Junchul ; Oh, Hyunok ; Kim, Sungchan ; Ha, Soonhoi

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
  • fYear
    2012
  • fDate
    3-7 June 2012
  • Firstpage
    664
  • Lastpage
    671
  • Abstract
    In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a non-optimized approach and the previous approach.
  • Keywords
    data flow graphs; evolutionary computation; memory architecture; multiprocessing systems; processor scheduling; storage management; EA-based technique; SDF applications; SDF graphs; SPM size limitation; SPM-based multicore architecture; code overlay overhead; data overlay overhead; evolutionary algorithm-based technique; memory latency; multiprocessor scheduling; nonoptimized approach; prefetching; scheduling problem; scratchpad memory; synchronous dataflow graphs; Delay; Multicore processing; Prefetching; Schedules; Tiles; Multiprocessor scheduling; memory overlay; multicore architecture; prefetching; scratch pad memory; synchronous dataflow;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4503-1199-1
  • Type

    conf

  • Filename
    6241577