DocumentCode
565247
Title
Goal-oriented stimulus generation for analog circuits
Author
Ahmadyan, Seyed Nematollah ; Kumar, Jayanand Asok ; Vasudevan, Shobha
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2012
fDate
3-7 June 2012
Firstpage
1018
Lastpage
1023
Abstract
We present a methodology to generate goal-oriented test cases for verifying nonlinear analog circuits. We use a learning-based approach to identify the goal regions in circuit´s state space. We use the information that we learn to guide the growth of Rapidly-exploring Random Trees (RRTs) towards these goal regions. Compared to previous approaches for test generation, our methodology generates several test cases of the circuit that are more concentrated in the relevant operating regions. We demonstrate the effectiveness of our approach on typical case studies. We show that our methodology can be used to generate test cases for undesirable behavior that was previously hard to detect.
Keywords
analogue circuits; electronic engineering computing; formal verification; learning (artificial intelligence); nonlinear network analysis; random processes; trees (mathematics); RRT; circuit state space; goal-oriented stimulus generation; goal-oriented test case generation; learning-based approach; nonlinear analog circuit verification; rapidly-exploring random trees; Algorithm design and analysis; Analog circuits; Clustering algorithms; Data structures; Integrated circuit modeling; Mathematical model; Trajectory; Pre-Si testing; Rapidly-exploring random trees;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-4503-1199-1
Type
conf
Filename
6241629
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