Flip chip power cycling system development and lead free bump power cycling reliability

In this paper, a novel power cycling system with thermal test vehicle design following the concept defined in JESD22-A122 standard has been established to better approximate field operating conditions. The test unit used in the system is to simulate real product, therefore it is not only package on board but also with an external fan. A closed-loop controller with power modules in this system is able to activate thermal test chip and external fan for power cycling heating and cooling profile tracking, in parallel data acquisition can monitor in-situ daisy chain resistance. In addition, this system is designed to perform power cycling test on multi-packages, which is beneficial to characterize power cycling reliability in chip-to-package and package-to-system level integration and product performance during technology development. An advanced Cu/low-K 16 × 14mm² silicon chip with 35 × 35 mm² - 1156L lead free bump flip chip BGA package was used with underfill material splits on pairing low, medium, and high Tg and modulus values. The effect of underfill properties (Tg, modulus) on SnAg lead free bump flip chip package power cycling reliability was characterized and verified by FEM (finite element method). Besides, the power cycling profile temperature range and temperature ramp rate effect was discussed and quantified by Weibull analysis. The results can provide useful guideline for chip to package integration even system design for further reliability enhancement.