• DocumentCode
    56591
  • Title

    Simultaneous fabrication of a through-glass interconnect via and a bump using dry film resist and submicron gold particles

  • Author

    Mimatsu, Hayata ; Mizuno, Jun ; Shoji, Shuji ; Kasahara, T. ; Shih, Kailing ; Nomura, Keigo ; Kanehira, Yukio ; Ogashiwa, Toshinori

  • Author_Institution
    Dept. of Nanosci. & Nanoengineering, Waseda Univ., Tokyo, Japan
  • Volume
    9
  • Issue
    8
  • fYear
    2014
  • fDate
    Aug. 2014
  • Firstpage
    532
  • Lastpage
    535
  • Abstract
    A process for the simultaneous fabrication of through-glass interconnect vias (TGVs) and gold (Au) bumps using dry film resist and submicron Au particles is proposed. A Ti/Pt/Au layer was sputtered on the top and bottom surfaces of glass vias to improve the adhesion between the glass substrate and submicron Au particles. The submicron Au particles filled the resist holes and glass vias fabricated by photolithography and by the two-electrode method, respectively, and were then sintered. The height and diameter of the fabricated Au bumps were about 20-25 and 200 μm, respectively. The Ti/Pt/Au layer on the surface of the glass substrate was removed by Ar ion milling to isolate each bump electrically. The resistance of a single Au bump and TGV was evaluated using the four-wire ohm method to be about 0.05 Ω. Furthermore, Au bump bonding was demonstrated. Fractured Au bumps and TGVs were observed by scanning electron microscopy after the bonded sample was peeled. It is expected that this fabrication process using a dry film resist and submicron Au particles will be useful in simple packaging processes to form glass interposer substrates or glass integrated circuit chips.
  • Keywords
    adhesion; electrical resistivity; gold; integrated circuit interconnections; integrated circuit packaging; photolithography; photoresists; platinum; scanning electron microscopy; sputter deposition; thin films; titanium; TGV; Ti-Pt-Au-SiO2; adhesion; bump bonding; dry film resist; four-wire ohm method; fractured bumps; glass integrated circuit chips; glass substrate; packaging processes; photolithography; scanning electron microscopy; sintering; sputter deposition; submicron gold particles; through-glass interconnect vias; two-electrode method;
  • fLanguage
    English
  • Journal_Title
    Micro & Nano Letters, IET
  • Publisher
    iet
  • ISSN
    1750-0443
  • Type

    jour

  • DOI
    10.1049/mnl.2014.0187
  • Filename
    6891915