DocumentCode :
566222
Title :
3D stacking using Cu-Cu direct bonding
Author :
Hu, Y.H. ; Liu, C.S. ; Lii, M.J. ; Rebibis, K.J. ; Jourdain, A. ; Manna, Antonio La ; Beyer, G. ; Beyne, E. ; Yu, C.H.
Author_Institution :
TSMC assignee at IMEC, Taiwan
fYear :
2012
fDate :
Jan. 31 2012-Feb. 2 2012
Firstpage :
1
Lastpage :
4
Abstract :
Cu-Cu bonding provides advantages such as cost effective process, fine pitch, and low resistance to advanced 3D IC technology. For 3D stacking, TSV Cu nail can be revealed by wafer backside process and used as interconnect between top and bottom die. No extra process like RDL (Re-Distribution Layer) and bumping are required, thus, μbump pitch is equivalent to TSVs pitch. Further there is no inter-metallic compound (IMC) layer formation and thus improve the mechanical reliability. In this work, we report the results achieved for 3D staking with Cu-Cu bonding by using TCB (Thermal Compression Bonding) process. Three different TSVs nail structures named No Nail, Flat Surface, and Dome Shape, respectively are choose to study the impact of nail structures to various TCB conditions. The TSVs have 5μm diameter with a minimum pitch of 10μm. Cross section SEM (Scanning Electron Microscope) is used to identify interface-bonding qualities. Electrical characterizations on TSV chains are also performed. Based on above specifics results, a best performing structure for TSVs nails is selected in term of electrical connections and good adhesions between dies. Finally, we propose some suggestions for future work on Cu-Cu bonding.
Keywords :
copper; integrated circuit bonding; scanning electron microscopy; three-dimensional integrated circuits; μbump pitch; 3D stacking; Cu-Cu; TCB process; TSV chains; TSV nail structures; TSV pitch; advanced 3D IC technology; bottom die; bumping; cost effective process; cross section SEM; direct bonding; dome shape; electrical characterizations; electrical connections; fine pitch; flat surface; interface-bonding qualities; low resistance; mechanical reliability; no nail; scanning electron microscope; size 5 mum; thermal compression bonding process; top die; wafer backside process;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
Type :
conf
DOI :
10.1109/3DIC.2012.6262944
Filename :
6262944
Link To Document :
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