TSV process solution for 3D-IC

Author

Toyoda, S. ; Shibata, A. ; Harada, M. ; Murayama, T. ; Sakuishi, T. ; Hatanaka, M. ; Morikawa, Y. ; Suu, K.

Author_Institution

Inst. of Semicond. & Electron. Technol., ULVAC, Inc., Shizuoka, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

5

Abstract

Through-silicon-via (TSV) process of which process temperature is less than 180 degree C (°C) has been accomplished by using ZrBO dielectric film and WN barrier film. Integration of ZrBO and WN, both being Carbon free, capable to deposit at low temperature and showing high barrier performance, would result in high reliability in Cu interconnect. The diameter of 5μm (Φ5μm) TSV was formed by anisotropie etching with non-Bosch process, which we call “scallop-free”, and the aspect ratio was about 10 (AR10). The sidewall roughness is below 15nm.

Keywords

boron compounds; dielectric thin films; etching; integrated circuit interconnections; integrated circuit reliability; three-dimensional integrated circuits; tungsten compounds; zirconium compounds; 3D-IC; Cu interconnect reliability; TSV process solution; WN barrier film; ZrBO-WN; anisotropic etching; dielectric film; high barrier performance; nonBosch process; scallop-free process; sidewall roughness; size 5 mum; temperature 180 degC; through-silicon-via process;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262945

Filename

6262945