TSV optimization for BEOL interconnection in logic process

Control of Cu extrusion and delamination due to CTE mismatch between Si and Cu is a big issue for high reliable TSV formation. In this paper we tried to find some methods to reduce Cu extrusion and to prevent TSV sidewall delamination. It is demonstrated that residual Cu extrusion height can be reduced by additional high temperature heat treatment before TSV CMP. And also Cu extrusion and delamination strongly depends on TSV dimension, which leads to the conclusion that smaller vias are preferred for better reliability.