Chip-level TSV integration for rapid prototyping of 3D system LSIs

Author

Hozawa, Kazuyuki ; Furuta, Futoshi ; Hanaoka, Yuko ; Aoki, Mayu ; Takeda, Kenichi ; Sakuma, Katsuyuki ; Lee, Kang Wook ; Fukushima, Takafumi ; Koyanagi, Mitsumasa

Author_Institution

Assoc. of Super-Adv. Electron. Technol. (ASET), Tokyo, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

4

Abstract

For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs.

Keywords

large scale integration; rapid prototyping (industrial); three-dimensional integrated circuits; 3D integration; 3D system LSI; TSV fabrication technology; TSV formation; chip level TSV integration; diced chip; rapid prototyping; substrate thinning; through silicon vias; Copper; Films; Resistance; Silicon; Through-silicon vias; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262952

Filename

6262952