A very low area ADC for 3-D stacked CMOS image processing system

This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC array. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. To achieve extremely low circuit area and low power dissipation, ADC designed in the prototype chip for fundamental evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. An implemented 9-bit prototype in a 90 nm CMOS technology occupies 100×100 μm², achieves an ENOB of 7.28 bit at a conversion rate of 4 MS/s. The power dissipation is 381μW with supply voltage of 1.0V and 4 MS/s conversion rate.