Coordinating 3D designs: Interface IP, standards or free form?

Author

Franzon, Paul D. ; Davis, W. Rhett ; Zhou, Zheng ; Priyadarshi, Shivam ; Hogan, Matthew ; Karnik, Tanay ; Srinavas, Ganapti

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

3

Abstract

Three dimensional integration technology introduces new complexities to design and particularly codesign. Additional complexity is added when one considers that the design needs to be “future-proof”. How do you ensure that the 3D chip stack will work for future chips within the stack, whose parameters are yet to be fully anticipated. This paper proposes that this be managed through an Interface IP approach Design blocks with associated properties that not only supports signaling and power delivery but also constraints that must be managed between chips both during design but also in-situ and as part of physical verification.

Keywords

IP networks; computer interfaces; electronic engineering computing; integrated circuit design; integration; three-dimensional integrated circuits; 3D chip stack; 3D coordinating design; dimensional integration technology; interface IP approach; power delivery;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262960

Filename

6262960