A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization

Author

Jiangfeng Wu ; Chun-Ying Chen ; Tianwei Li ; Lin He ; Wenbo Liu ; Wei-Ta Shih ; Tsai, Shauhyuarn Sean ; Binning Chen ; Chun-Sheng Huang ; Hung, Bryan Juo-Jung ; Hung, Hing T. ; Jaffe, Sam ; Loke Kun Tan ; Hung Vu

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

48

Issue

8

fYear

2013

fDate

Aug. 2013

Firstpage

1818

Lastpage

1828

Abstract

This paper introduces multiplying digital-to-analog converter (MDAC) equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain, settling, and other dynamic errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240-mW 2.1-GS/s ping-pong pipeline ADC in 40-nm CMOS where MDAC RA power is reduced from 175 to 53 mW by 70%. The ADC achieves 58 dB SNR and 52 dB SNDR.

Keywords

CMOS digital integrated circuits; FIR filters; amplifiers; analogue-digital conversion; digital-analogue conversion; pipeline processing; MDAC RA bandwidth; MDAC RA power; MDAC equalization; MDAC gain; MDAC residue amplifier bandwidth; SNDR; SNDR pipeline ADC; SNR; digital correction technique; multiplying digital-to-analog converter equalization; ping-pong pipeline ADC power; power 175 mW to 53 mW; power 240 mW; sampling frequency; size 40 nm; sub-ADC output samples; successive digital FIR filters; Accuracy; Bandwidth; Finite impulse response filters; Mathematical model; Pipelines; Switches; Transfer functions; Analog-to-digital converter (ADC); CMOS; digital correction; equalization; multiplying digital-to-analog converter (MDAC); pipeline; residue amplifier (RA);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2259013

Filename

6515198