6 Tbps/W, 1 Tbps/mm2, 3D interconnect using adaptive timing control and low capacitance TSV

We describe a Through Silicon Via (TSV) interconnect for multi-layer stacked chips by using a low capacitance TSV and by introducing a novel circuit design with an adaptive timing control. Studying effects of TSV parasitic capacitances on the interconnect performance, a low capacitance TSV was designed and was experimentally confirmed that the capacitance was 90 fF/TSV. To enhance the performance, an adaptive timing control was applied to a low voltage swing circuit. Feeding back information on the TSV capacitance to an output voltage control as timing signals, difficulties in timing designs resulting from variations of TSV capacitances were resolved. The circuit has scalability to the number of stacked TSVs and a robustness against process-to-process variations of TSV capacitances. The power efficiency of at least 27% is enhanced using the low voltage swing circuit. A data-rate of 1 Tbps/mm² and the highest power efficiency of 6 Tbps/W were experimentally confirmed using 3D-stacked chips with the low capacitance TSVs.