ESD protection networks for 3D integrated circuits

Author

Rosenbaum, Elyse ; Shukla, Vrashank ; Keel, Min-Sun

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

7

Abstract

The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. The magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package level. It is also affected by the type of package being used. Small voltage clamping devices may be placed at inter-die receivers to mitigate the risk of gate dielectric breakdown. New ESD rule checking tools are needed for 3D-IC design automation.

Keywords

electric breakdown; electrostatic discharge; integrated circuit design; integrated circuit modelling; integrated circuit packaging; three-dimensional integrated circuits; 3D integrated circuits; 3D-IC design automation; ESD protection networks; ESD rule checking tools; charged device model; gate dielectric breakdown; ground distribution network; interdie receivers; interdie signal interfaces; overvoltage stress; package level; small voltage clamping devices; Clamps; Discharges (electric); Electrostatic discharges; Integrated circuit modeling; Receivers; Stress; Through-silicon vias; Charged Device Model; Electrostatic discharge;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262965

Filename

6262965