DocumentCode :
566256
Title :
Vias-last process technology for thick 2.5D Si interposers
Author :
Vick, Erik ; Goodwin, Scott ; Cunnigham, Garry ; Temple, Dorota S.
Author_Institution :
Center for Mater. & Electron. Technol., RTI Int., Research Triangle Park, NC, USA
fYear :
2012
fDate :
Jan. 31 2012-Feb. 2 2012
Firstpage :
1
Lastpage :
4
Abstract :
Relative to traditional chip-to-substrate or chip-to-PCB packaging, solutions utilizing 2.5D silicon interposers can provide significantly higher I/O densities, resulting in reduced size, lower power consumption, and higher functionality [1,2]. One example of an advanced packaging application enabled by Si interposers is an embedded computing module (ECM) illustrated in Figure 1. Benefits of this advanced electronic packaging approach include (1) reduction in size by a factor of 2-3, (2) reduction in system power, and (3) elimination of on-die termination resistors [3].
Keywords :
elemental semiconductors; integrated circuit packaging; silicon; three-dimensional integrated circuits; ECM; I/O densities; Si; advanced electronic packaging approach; chip-to-PCB packaging; chip-to-substrate packaging; embedded computing module; on-die termination resistors; power consumption; silicon interposers; vias-last process technology; Contacts; Fabrication; Metallization; Resistance; Silicon; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
Type :
conf
DOI :
10.1109/3DIC.2012.6262990
Filename :
6262990
Link To Document :
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