In-line metrology and inspection for process control during 3D stacking of IC´s

New challenges for wafer metrology solutions have evolved with 3D-IC manufacturing technology. 3D-IC technology allows stacking single chips, electrically connecting them in the vertical direction, and then forming a chip structure with significant advantages over traditional chips. Wafer level 3D integration is a system level architecture in which multiple layers of planar devices are stacked and interconnected through the silicon. The industry is moving past the R&D phase fast. However, before the 3D-stacking of IC´s becomes a mainstream process numerous metrology issues need to be solved. In this paper we discuss the critical in-line metrology needs during the manufacture of 3D SIC´s. We show how TSV depth variations, glue layer defects and grinding issues require monitoring for a successful 3D integration.