DocumentCode
566274
Title
Evaluation of wafer level Cu bonding for 3D integration
Author
Kang, Sung-Geun ; Kim, Youngrae ; Kim, Eun-Sol ; Lim, Naeun ; Jeong, Teakgyu ; Lee, Jieun ; Kim, Sarah Eunkyung ; Kim, Sungdong
Author_Institution
Microsyst. Packaging Center, Nowongu, South Korea
fYear
2012
fDate
Jan. 31 2012-Feb. 2 2012
Firstpage
1
Lastpage
2
Abstract
Alignment from an aligner, bond spacer removal during bonding, and wafer warpage are found to be the influential issues for the misalignment in wafer level bonding process. Also, Cu surface pre-treatment, thermo-compression bonding conditions such as temperature, pressure, ambient gas, annealing time, and Cu CMP process affect significantly a bonding quality.
Keywords
chemical mechanical polishing; copper; integrated circuit bonding; three-dimensional integrated circuits; wafer level packaging; 3D integration; CMP process; Cu; bond spacer removal; surface pretreatment; thermo-compression bonding conditions; wafer level bonding process; wafer warpage; Bonding; Rough surfaces; Semiconductor device reliability; Silicon; Stacking; Surface roughness; Surface treatment;
fLanguage
English
Publisher
ieee
Conference_Titel
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location
Osaka
Print_ISBN
978-1-4673-2189-1
Type
conf
DOI
10.1109/3DIC.2012.6263014
Filename
6263014
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