Multi-step approach for thermal optimization of 3D-IC and package

The move from 2D to 3D integration of digital electronic systems (e.g. a multiprocessor with memory) offers a great deal of advantages and is clearly the most promising option for designing future systems. However, the density of the heat dissipation spots is much higher in 3D systems. In the design of such systems, the temperature distribution of the whole system including the package solution must be consider and optimized. In this paper a common optimization approach for early (pathfinding) and later (floorplan) timing and thermal optimization is presented. The developed optimization engine can be used - with different inputs - for both steps (pathfinding and floorplanning). The developed flow is successfully applied to a 3D VLIW-processor.