Title :
3D-Scalable Adaptive Scan (3D-SAS)
Author :
Syed, Uzair Shah ; Chakrabarty, Krishnendu ; Chandra, Anshuman ; Kapur, Rohit
Author_Institution :
Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
fDate :
Jan. 31 2012-Feb. 2 2012
Abstract :
Performance requirements and interconnect bottlenecks associated with technology scaling have led to the development of 3D stacked ICs (3D-SICs) based on through-silicon vias (TSVs). Testing of 3D-SICs is challenging due to severely limited physical access. In a limited access situation, test compression offers a promising solution to the problem of testing 3D ICs. Scalable Adaptive Scan (SAS) requires a very narrow scan interface. This paper integrates SAS with known core test-wrapper designs and emerging die wrapper methods to provide an effective solution to the problem of testing 3D-SICs.
Keywords :
integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D stacked IC; 3D-SAS; 3D-SIC testing; 3D-scalable adaptive scan; die wrapper; interconnect bottlenecks; narrow scan interface; technology scaling; through-silicon vias; Codecs; Discrete Fourier transforms; Pins; Probes; Synthetic aperture sonar; Testing; Through-silicon vias; 3D-SIC testing; DFT; SAS; TSV; compression;
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
DOI :
10.1109/3DIC.2012.6263043
