Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies

Author

Ikeuchi, Katsuyuki ; Takamiya, Makoto ; Sakurai, Takayasu

Author_Institution

Univ. of Tokyo, Tokyo, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

5

Abstract

A Through Silicon Capacitive Coupling (TSCC) interface enabling face-to-back capacitive coupling data transfer for 3D stacked dies is proposed. TSCC has three features, (1) it allows stacking more than three chips, (2) it enables easy access to the bonding pads for DC power supplies, and (3) it enables the capacitive coupling pads to be used as bonding pads. TSCC channel models are assumed and design guidelines are given for transceiver design. A transceiver designed and fabricated in 0.18μm CMOS successfully communicates through a 400μm silicon substrate at 200Mbps. It is also shown that thinning the chip will reduce the area overhead of the TSCC pad.

Keywords

CMOS integrated circuits; bonding processes; elemental semiconductors; integrated circuit design; power supply circuits; silicon; stacking; three-dimensional integrated circuits; transceivers; 3D stacked die; CMOS technology; DC power supply; Si; TSCC channel model interface; bit rate 200 Mbit/s; bonding pad; capacitive coupling data transfer; capacitive coupling pad; chip thinning; size 0.18 mum; size 400 mum; through silicon capacitive coupling channel model interface; transceiver design; Bonding; Couplings; Inverters; Logic gates; Receivers; Silicon; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6263045

Filename

6263045