DocumentCode :
566623
Title :
Improved Static Desynchronization scheme for Clos-network switches
Author :
Chao, Che-Hsi ; Hsu, YarSun
Author_Institution :
Dept. of Electr. Eng., Nat. Tsinghua Univ., Hsinchu, Taiwan
Volume :
2
fYear :
2012
fDate :
24-26 April 2012
Firstpage :
659
Lastpage :
664
Abstract :
A Clos-network is widely recognized as a scalable switch. Previously proposed dispatching schemes such as concurrent round-robin-based dispatching schemes (CRRD) are able to achieve high throughput. However, speed-up memory and dispatching time are impractical when a switch size is increased. First, this paper presents a novel Memory-Space-Memory (MSM) without speed-up memory. Second, this paper introduces two dispatching schemes. Both schemes are practical to implement because dispatching time is feasible with current technologies. The first is a simple scheme called Static Desynchronization (SD). SD is able to achieve high throughput under uniform traffic by the static desynchronization effect. The second scheme is the Improved Static Desynchronization (ISD) dispatching scheme to overcome the inflexible property of the SD scheme. ISD based on SD is used to develop a medium structure and desynchronized pointers to improve the matching ratio. This study also details how to use the desynchronization effect to obtain 100% throughput under any type of traffic pattern.
Keywords :
Complexity theory; Degradation; Hardware; IP networks; ISO standards; Registers; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computing Technology and Information Management (ICCM), 2012 8th International Conference on
Conference_Location :
Seoul, Korea (South)
Print_ISBN :
978-1-4673-0893-9
Type :
conf
Filename :
6268581
Link To Document :
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