DocumentCode
566705
Title
Mapping of cores on to diagonal mesh-based network-on-chip
Author
Saffari, M. ; Lotfi, S. ; Jafarzadeh, N. ; Afzali-Kusha, A.
Author_Institution
Dept. of Comput. Eng., Islamic Azad Univ., Arak, Iran
fYear
2012
fDate
19-21 June 2012
Firstpage
233
Lastpage
238
Abstract
In this work, a genetic solution to map cores onto the diagonal mesh-based network-on-chip architecture is proposed. We take the communication cost as the optimization function of the mapping algorithm based on the genetic algorithm. We also, modify an existing deadlock free routing algorithm for diagonal mesh. Although, diagonal mesh is similar to the traditional mesh topology, it generally has better performance, power consumption, and saturation points than mesh and reduces the hop count between the directly connected cores in the core graph. The results of the proposed technique are compared with those of the traditional mesh based network on chips. The comparative study is performed for VOPD and MPEG-4 which are two complex benchmarks. The results show that the combination of diagonal mesh topology, genetic algorithm based mapping technique, and deadlock free routing algorithm outperforms the mesh-based NoCs.
Keywords
genetic algorithms; logic circuits; microprocessor chips; network routing; network topology; network-on-chip; MPEG-4; VOPD; communication cost; complex benchmarks; core graph; cores mapping; deadlock free routing algorithm; diagonal mesh topology; diagonal mesh-based network-on-chip architecture; directly connected cores; genetic algorithm-based mapping technique; mesh-based NoC; optimization function; power consumption; saturation points; Switches; Transform coding; GMAP; Mapping; communication coast; diagonal mesh; genetic algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computing (MECO), 2012 Mediterranean Conference on
Conference_Location
Bar
Print_ISBN
978-1-4673-2366-6
Type
conf
Filename
6268967
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