A synchronous compression method based on compressed sensing for time-interleaved sampling

The time-interleaved sampling technique, which can reduce the requirement to the speed of ADCs by using parallel operation of multiple ADCs, has become a practical solution for high speed data acquisition. To further reduce the quantity of the acquired data for frequency-sparse signals, this paper presents a new data acquisition and compression method combining time-interleaved sampling technique with Compressed Sampling (CS) theory. We implement synchronous data compression using Field Programmable Gate Array (FPGA) device, in which the asynchronous data streams are first synchronized through multistage buffering method and then compressed by CS approach. An important strength of this method lies in that the entire design is synchronized by a common clock, which allows the circuit to work at a high rate. From the perspective of data stream, we obtain a compressed data steam at a sub-Nyquist rate which reduces the load of storage and transmission significantly. The simulation experiments verify that the original signal can be recovered exactly from the compressed data with overwhelming probability.