• DocumentCode
    568600
  • Title

    Delay Analysis for an N-Input Current Mode Threshold Logic Gate

  • Author

    Dara, Chandra Babu ; Haniotakis, Themistoklis ; Tragoudas, Spyros

  • Author_Institution
    ECE Dept., Southern Illinois Univ., Carbondale, IL, USA
  • fYear
    2012
  • fDate
    19-21 Aug. 2012
  • Firstpage
    344
  • Lastpage
    349
  • Abstract
    A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.
  • Keywords
    CMOS logic circuits; delays; logic gates; CMOS gates; delay analysis method; exhaustive SPICE simulations; n-input current mode threshold logic gate; small integer weights; threshold logic functions; Boosting; Capacitance; Clocks; Delay; Logic gates; SPICE; Transistors; Threshold logic gates; current mode; operating speed; sensor sizing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on
  • Conference_Location
    Amherst, MA
  • ISSN
    2159-3469
  • Print_ISBN
    978-1-4673-2234-8
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2012.34
  • Filename
    6296497
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=568600