Study of multipliers in residue arithmetic using programmable logic

Residue number system (RNS) has long been proposed to perform arithmetic computations with integers at high speed, because this system does not need to propagate the carry. The RNS main application is in digital signal processing. Recently, field programmable logic (FPL) devices have become a technology for developing applications based on residue arithmetic. Because adders and multipliers are the core of most of the circuits based on RNS, the objective of this work is to characterize the performance of RNS multipliers when they are implemented in programmable logic. This paper includes various types of multipliers for modules from 3 to 256, the adders have already been treated. To build the hardware Altera FLEX10K and MAX7000 devices were used, the first ones performed the logic circuit synthesis using lookup tables (LUT) and the second ones by sum of product terms or Min-Terms (MT).