Area efficient reconfigurable architecture for current control loop of a servo controller

The paper presents a novel reconfigurable architecture for the current control loop for controlling AC servo motors. The various functions of current control loop namely vector control algorithm, current sampling, space vector pulse width modulation and Proportional plus Integral (PI) algorithm are implemented as separate modules. The modular approach of implementation identifies multiple usage of the Coordinate Rotation Digital Computer (CORDIC) block. The paper reports the reduction in the area consumption by reusing the CORDIC block without affecting the speed of operation. The FPGA (Field Programmable Gate Array) implementation proposed in this paper also provides a real-time and online percentage duty cycle calculation scheme for variable frequency PWM wave. The proposed scheme implements division using CORDIC so that a small amount of FPGA area is consumed. This allows other modules that are using the duty cycle input to be implemented on the same FPGA. Modes in which CORDIC is used are: Rotation mode for calculating Park and inverse Park transform and Linear mode for calculating division. Pulse width and time period of the input Pulse Width Modulated (PWM) wave are measured using the conventional counter method. The paper proposes a novel event generation scheme for operating these counters. The proposed scheme is also useful where a jitter exists in time period of input PWM wave. Another contribution of this paper is in identifying common calculations in Space Vector Pulse Width Modulation (SVPWM) generation in order to save FPGA area.