Title :
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI
Author :
Sugawara, Toshiki ; Suzuki, Daisuke ; Katashita, Toshihiro
Author_Institution :
Inf. Technol. R & D Center, Mitsubishi Electr. Corp., Kamakura, Japan
Abstract :
Circuit simulation method for Fault Sensitivity Analysis (FSA) is proposed. The simulation can be used both for (i) security evaluation before fabrication and (ii) investigation of leak mechanism. The proposed method extracts fault sensitivity data from post place-and-route logic simulation results, thus it can easily be integrated with conventional LSI design flow. As a proof of concept, the proposed method is applied to netlist of an AES implementation on 130-nm SASEBO LSI. In the experiment, key recovery attack is successfully recreated using simulated data of a standard implementation (AES_Comp). In addition, to bridge a gap between the simulation and real measurement, we model the effect of induced timing jitter (measurement noise) on the resulting correlation.
Keywords :
circuit simulation; cryptography; fault diagnosis; integrated circuit design; integrated circuit measurement; integrated circuit noise; large scale integration; logic circuits; logic simulation; network routing; timing jitter; AES implementation; FSA; SASEBO LSI; circuit simulation method; cryptographic LSI design flow; fault sensitivity analysis; fault sensitivity data extraction; key recovery attack; leak mechanism investigation; noise measurement; post place-and-route logic simulation; security evaluation; size 130 nm; timing jitter; Analytical models; Conferences; Data models; Fluid flow measurement; Histograms; Indexes; Timing; Circuit Simulation; Fault Sensitivity Analysis; Fault injection attacks; Side-channel attacks;
Conference_Titel :
Fault Diagnosis and Tolerance in Cryptography (FDTC), 2012 Workshop on
Conference_Location :
Leuven
Print_ISBN :
978-1-4673-2900-2
DOI :
10.1109/FDTC.2012.17
