DocumentCode
571475
Title
An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks
Author
Endo, Sho ; Li, Yang ; Homma, Naofumi ; Sakiyama, Kazuo ; Ohta, Kazuo ; Aoki, Takafumi
Author_Institution
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
fYear
2012
fDate
9-9 Sept. 2012
Firstpage
95
Lastpage
102
Abstract
In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li´s countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.
Keywords
application specific integrated circuits; cryptography; field programmable gate arrays; AES module; ASIC; CDB; DFA attack; FSA attack; Li countermeasure concept; WDDL; configurable delay blocks; cryptographic modules; differential fault analysis; fault attack; fault sensitivity analysis; hardware overhead; masked AND-OR; overhead minimization; post-manufacture configuration; prototype FPGA implementation; redundancy calculation; secret information; setup time violation fault; wave dynamic differential logic; Circuit faults; Clocks; Cryptography; Delay; Doped fiber amplifiers; Sensitivity; AES; Configurable delay block; Countermeasures; Fault Sensitivity Analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Fault Diagnosis and Tolerance in Cryptography (FDTC), 2012 Workshop on
Conference_Location
Leuven
Print_ISBN
978-1-4673-2900-2
Type
conf
DOI
10.1109/FDTC.2012.12
Filename
6305233
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