Comparison of receiver equalization using first-order and second-order Continuous-Time Linear Equalizer in 45 nm process technology

The gap between on-chip and off-chip communication speed has become wider as the IC process technology continues to shrink in order to increase the chip performance. The speed of on-chip circuit has outperformed the off-chip communication speed. Therefore, the performance threshold of a system which consists of multiple IC´s is limited by the off-chip communication speed. I/O interfaces such as PCI-Express, USB 3.0, and DDR3 are designed to bridge the gap by introducing high-speed transceiver system which typically operates at Giga-Hertz range. However, legacy copper interconnect on a motherboard backplane cannot support data rate. As a result, integrity of the signal is impaired with nonideal effects introduced by the channel. Continuous-Time Linear Equalizer (CTLE) is used at the receiver front-end to compensate the high-frequency losses introduced by the channel. The implementation of CTLE is normally limited to first-order. Second-order CTLE offers the advantage of incremental peaking gain when dealing with channel of high losses. Therefore, in this paper, the characteristics and theoretical circuit analysis of first-order and second-order CTLEs are presented. Both equalizers are designed to address a 5-Gb/s data rate transmission. An arbitrary 20-inch channel is used as test bench to compare the performance of the two equalizers. Simulation results show improvement in receive eye voltage opening and insertion loss for second-order CTLE but with degradation in terms of receive eye time opening, jitter, and amplitude noise.