DocumentCode :
572402
Title :
The impact of memory subsystem resource sharing on datacenter applications
Author :
Tang, Lingjia ; Mars, Jason ; Vachharajani, Neil ; Hundt, Robert ; Soffa, Mary Lou
Author_Institution :
Univ. of Virginia, Charlottesville, UT, USA
fYear :
2011
fDate :
4-8 June 2011
Firstpage :
283
Lastpage :
294
Abstract :
In this paper we study the impact of sharing memory resources on five Google datacenter applications: a web search engine, bigtable, content analyzer, image stitching, and protocol buffer. While prior work has found neither positive nor negative effects from cache sharing across the PARSEC benchmark suite, we find that across these datacenter applications, there is both a sizable benefit and a potential degradation from improperly sharing resources. In this paper, we first present a study of the importance of thread-to-core mappings for applications in the datacenter as threads can be mapped to share or to not share caches and bus bandwidth. Second, we investigate the impact of co-locating threads from multiple applications with diverse memory behavior and discover that the best mapping for a given application changes depending on its co-runner. Third, we investigate the application characteristics that impact performance in the various thread-to-core mapping scenarios. Finally, we present both a heuristics-based and an adaptive approach to arrive at good thread-to-core decisions in the datacenter. We observe performance swings of up to 25% for web search and 40% for other key applications, simply based on how application threads are mapped to cores. By employing our adaptive thread-to-core mapper, the performance of the datacenter applications presented in this work improved by up to 22% over status quo thread-to-core mapping and performs within 3% of optimal.
Keywords :
Internet; cache storage; computer centres; multi-threading; resource allocation; search engines; Bigtable; Google datacenter applications; PARSEC benchmark suite; Web search engine; adaptive approach; application characteristics; bus bandwidth; cache sharing; content analyzer; heuristics-based approach; image stitching; memory subsystem resource sharing; performance improvement; protocol buffer; thread colocation; thread-to-core mappings; Bandwidth; Instruction sets; Multicore processing; Resource management; Sockets; Topology; Yarn; Experimentation; Measurement; Performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture (ISCA), 2011 38th Annual International Symposium on
Conference_Location :
San Jose, CA
ISSN :
1063-6897
Print_ISBN :
978-1-4503-0472-6
Type :
conf
Filename :
6307765
Link To Document :
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