Title :
Relation between HCI-induced performance degradation and applications in a RISC processor
Author :
Bertolini, C. ; Heron, O. ; Ventroux, N. ; Marc, F.
Author_Institution :
LIST, CEA, Gif-sur-Yvette, France
Abstract :
Die shrinking combined with the non-ideal scaling of voltage increases the probability of MOS transistors to encounter hot carrier injections (HCI). This failure mechanism causes a performance degradation of digital ICs. The evaluation of timing degradations becomes a must-have to ensure the expected time-to-market and IC lifetime early in the design flow. In this paper, we present a design/verification flow at front-end from which we accurately analyze the impact of instruction-set architecture on processor timings. We show results on a RISC processor named AntX and designed in a 40 nm TSMC technology. Using typical-case scenarios can increase the maximum operating frequency by 15% on average compared to a worst-case scenario, while considering the same lifetime. We also identify that the shift operations cause the highest timing degradations along the long processor paths.
Keywords :
hot carriers; integrated circuit design; microprocessor chips; reduced instruction set computing; timing circuits; AntX RISC processor timing application; HCI-induced performance degradation; IC lifetime design flow; MOS transistor; TSMC technology; design-verification front-end flow; die shrinking; digital IC; failure mechanism; hot carrier injection; instruction-set architecture impact analysis; maximum operating frequency; nonideal voltage scaling; size 40 nm; time-to-market expection; timing degradation evaluation; Degradation; Human computer interaction; Logic gates; Propagation delay; Stress; Timing; Transistors;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
Conference_Location :
Sitges
Print_ISBN :
978-1-4673-2082-5
DOI :
10.1109/IOLTS.2012.6313843
