DocumentCode
573615
Title
Algorithmic techniques for robust applications
Author
Kumar, Rakesh
Author_Institution
Univ. of Illinois, Champaign, IL, USA
fYear
2012
fDate
27-29 June 2012
Firstpage
168
Lastpage
168
Abstract
Summary form only given. Much recent research suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to as stochastic processors. In this talk, I will discuss three approaches for building applications for such processors. The first approach relies on relaxing the correctness of the application based upon an analysis of application characteristics. The second approach relies upon detecting and then correcting faults within the application as they arise. The third approach transforms applications into more error tolerant forms. In this paper, we show how these techniques that enhance or exploit the error tolerance of applications can yield significant power and energy benefits when computed on stochastic processors.
Keywords
fault diagnosis; fault tolerance; integrated circuit reliability; algorithmic techniques; application characteristic analysis; error tolerant; fault correction; fault detection; fault tolerance; future processors; relaxed constraints; stochastic processors; Abstracts; Buildings; Educational institutions; Program processors; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
Conference_Location
Sitges
Print_ISBN
978-1-4673-2082-5
Type
conf
DOI
10.1109/IOLTS.2012.6313865
Filename
6313865
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