A novel synchronization method for DS-CDMA systems

Code division multiple access (CDMA) has been proven to be a promising spread-spectrum multiple access technique due to its advantages such as anti-interference capability and implementation versatility. However, the problem of the receiver side synchronization at the sub-chip scale can significantly increase the decoding error rate, just as the carrier frequency offset (CFO) problem does to the OFDM systems. So far the use of faster sampling clock at the receiver analog-to-digital converter (ADC) is generally thought to improve the receiving performance and has been implemented in practical communication hardware such as the STEL-2000A CDMA chip. In this paper we show that the traditional use of such scheme can introduce interchip interference that causes an error floor irrespective of the sampling rate. We further propose a novel synchronization method that uses a digital filter bank to automatically seek out the best synchronization solution. Simulation results show that the proposed method performs almost as good as the case of perfect synchronization and far better than when there is a clock disparity. The proposed algorithm is also implemented in field programmable gate array (FPGA) and compared with the traditional approach to pave the way for its practical chip-level implementation.