• DocumentCode
    57447
  • Title

    Stacking Graphene Channels in Parallel for Enhanced Performance With the Same Footprint

  • Author

    Franklin, Aaron D. ; Oida, Soushi ; Farmer, Damon B. ; Smith, Joseph T. ; Han, S.-J. ; Breslin, Chris M. ; Gignac, Lynne

  • Author_Institution
    IBM T. J. Watson Research Center, Yorktown Heights, NY, USA
  • Volume
    34
  • Issue
    4
  • fYear
    2013
  • fDate
    Apr-13
  • Firstpage
    556
  • Lastpage
    558
  • Abstract
    Using the unique ability of graphene to be transferred to virtually any surface, field-effect transistors are demonstrated with vertically stacked graphene channels that are electrically connected in parallel. The graphene in each layer is double gated, with all gates in the stack connected to a common gate electrode. We show that the performance of these devices scales linearly with the number of stacked graphene channels at rates of approximately 500 \\mu\\hbox {A}/\\mu\\hbox {m} and 200 \\mu\\hbox {S}/\\mu\\hbox {m} per layer for the on-current and peak transconductance, respectively. This demonstration reveals the ability to employ graphene in a novel fashion for tuning and amplifying the performance of a transistor without changing the device footprint.
  • Keywords
    Dielectrics; Graphene; Logic gates; Performance evaluation; Scanning electron microscopy; Transconductance; Transistors; Double gate; field-effect transistor (FET); graphene; parallel channels; stacked;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2013.2242428
  • Filename
    6461911