Systematic large-signal verification procedure for mm-wave SiGe bipolar transistors

This paper describes a systematic large-signal verification procedure for mm-wave SiGe bipolar transistors. The verification paradigm is composed out of three complementary procedures: modeling of the intrinsic device(s), collecting measured data at the tips of probes and de-embedding the test fixture from measured data. The procedure is demonstrated for single and multi-device structures at two distinct operating frequencies, namely 900MHz and 30GHz. The verification between the measured and simulated data, reveals an accuracy of .3dB and 7% for respectively output power level and efficiency. Based on this verification procedure, a realistic overview of device performance describes in terms of PAE as function of Po over various frequencies and device-sizes, is extracted.