A Uniform Partitioning Method for Mono-Instruction Set Computer (MISC)

As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture.