A CMOS divider family for high frequency wireless localization systems

This paper presents a family of divider structures for use in high frequency wireless localization systems. All the structures can be realized in CMOS technology to reduce costs and power consumption. Different divider structures from static to programmable dividers and their combinations are presented. By combining CMOS logic and true-single phase clock (TSPC) logic, different dividers with low-power consumption and high operation speed for wireless localization systems can be realized. All designs were implemented in an 130 nm CMOS process. Measurement results indicates a maximum operating frequency from 10 GHz to 22 GHz for the designs. These results are compared to other state of the art dividers, showing the good performance of this designs relating to operating frequency and power consumption.