Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test

Circuits designed and fabricated with nanometer-scale technology are increasingly sensitive to power ground noise across a wide frequency range, thus necessitating a strict examination of circuit robustness against noise during manufacturing tests. Conventional at-speed testing techniques possibly result in the escape of marginal timing failures, as they are unable to account for the impact of middle- and low-frequency noise on circuit timing. To address this challenge, we propose, in this paper, a novel multi-functional-cycle test scheme that targets the noise-induced failures on critical paths of the circuit. The proposed technique explores the noise profile of at-speed functional cycles and approximates it in delay testing through the application of multiple capture operations, thus maximally detecting the timing failures that potentially take place under the worst case functional mode noise. The noise impact of individual devices on the critical paths is characterized through simulations on the power mesh model extracted from the circuit layout. This enables a computationally efficient yet SPICE-accurate estimation of the compound noise profile of the test pattern through the linear superposition of individual ones. Guided by this noise estimation technique, a test pattern transformation flow is proposed to maximize the noise in pseudo-functional test operations. Simulation results show that the proposed scheme can examine the effect of wide-bandwidth noise and thus perform a much more rigorous testing on critical paths than conventional delay testing schemes, thereby significantly improving test quality.