Digital block design of MIMO hardware simulator for LTE applications

This paper presents new frequency domain and time domain architectures for the digital block of a hardware simulator of MIMO propagation channels, with 3GPP TR 36.803 channel models test, for LTE applications. The hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment, thus making it possible to ensure the same test conditions in order to compare the performance of various equipments. After the description of the general characteristics of the hardware simulator, the new architectures of the digital block are presented and designed on a Xilinx Virtex-IV FPGA. Their accuracy and latency are analyzed. 3GPP TR 36.803 channel models test are given in details.