SOC design and FPGA implementation of Digital TV receiver

This paper proposes a System-on-chip (SoC) Architecture Design for real-time Digital TV receiver. The SoC includes RF interface, a Host Processor, a Physical Layer and Ethernet interface. The Physical Layer itself consists of Baseband Processing modules based on DVB-T standard which includes 2048-point FFT/IFFT, Channel Decoder, Synchronizer, Equalizer, Demodulator, etc. The SoC utilizes a 32-bit RISC based processor acting as the Host Processor. Both Processor and Physical layer works on 32 MHz clock cycle to ensure low power consumption. A real-time OS based on eCos is also used for controlling the Physical Layer and interfaces in a real-time basis. The system is implemented using FPGA and has been verified capable of receiving a realtime video transmitted by a standard digital TV transmitter/modulator.